1. Field of the Invention
This invention relates to a semiconductor integrated circuit that controls latch operations of plural latch circuits, by plural synchronous signals and more particularly to a semiconductor integrated circuit in which a latch circuit is composed of a master latch and a slave latch.
2. Description of Related Art
FIG. 1 shows a circuit diagram of structures of master latch and slave latch of a conventional semiconductor integrated circuit which was presented in IEEE JOURNAL OF SOLIDSTATE CIRCUIT, Vol. SC-22, No. 4, Aug., 1987 "A ScarceState-Transition Viterbi-Decorder VLSI for Bit Error Correction" pp. 578. Numeral 1 in the figure shows a master latch, and an output terminal Q.sub.1 of the master latch 1 is connected to a data terminal D.sub.2 of a slave latch 2. A synchronous signal, first clock .phi..sub.1, is applied to a clock terminal CP.sub.1 of the master latch 1, and a synchronous signal, second clock .phi..sub.2, which does not overlap the first clock .phi..sub.1, to a clock terminal CP.sub.2 of the slave latch 2, respectively. A clear signal CLR is applied to a reset terminal R of the master latch 1 and the slave latch 2, and when it is "L", the master latch 1 and the slave latch 2 are reset. An output from a logic circuit 3 is applied to a data terminal D.sub.1 of the master latch 1.
The logic circuit 3 comprises an inverter 31 to which a control signal PS is applied, an AND gate 32 to which the output of inverter 31 and a control signal M.sub.0 are applied, an AND gate 33 to which control signals PS and M.sub.1 are applied and a NOR gate 34 to which the outputs of AND gates 32 and 33 are applied. An output data A of the NOR gate 34 is applied to the data terminal D.sub.1 of the master latch 1. The truth table of outputs of the logic circuit 3 is shown as in Table 1.
TABLE 1 ______________________________________ M.sub.0 M.sub.1 PS A ______________________________________ 0 0 0 1 1 1 0 1 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 0 ______________________________________
Operations of conventional master and slave latch circuits composed in such manner are described below.
FIG. 2 is a timing chart showing operations of master and slave latch circuits. In order to describe general latch operations, suppose the clear signal CLR="H" here.
As shown in FIG. 2, if the output data A of the logic circuit 3 has changed before the first clock .phi..sub.1 changes from "H" to "L", the output data A is latched by the master latch 1 until the first clock .phi..sub.1 changes from "H" to "L". In succession, when the second clock .phi..sub.2 changes from "L" to "H", data from the output terminal Q.sub.1 of the master latch 1 is sent to the slave latch 2. This further becomes changes of output data from the output terminals Q.sub.1 and Q.sub.2 / of the slave latch 2. After the changes, the second clock .phi..sub.2 changes from "H" to "L", and the conditions do not change until the changed output data of the master latch 1 is sent to the slave latch 2.
In the conventional master and slave latches shown in FIG. 1, in the case that it is not required to feed data to the master latch 1, the first clock .phi..sub.1 generally maintains the disable state, that is, the logic "L" state, as shown in FIG. 2. Generally, the first clock .phi..sub.1 is generated by a logical product of an enable signal, not shown, which operates the latch circuit and a clock, and thus the disable state is maintained. Here supposing the first clock .phi..sub.1 comes to be disabled after the time (t.sub.n+1) as shown in FIG. 2, the output data of the master latch 1 does not change from the state of the time (t.sub.n) after the time (t.sub.n+1). In such case, although the second clock .phi..sub.2 which is supplied to the slave latch 2 is not required, it is continuously supplied.
In a semiconductor integrated circuit, specifically that of microprocessors and the like, although there are generally plural master and slave latch circuits in shapes of register array and counter, new data is not always inputted to all the master latches. In the case that it is not required to input new data to a master latch, data from the master latch is not required to be inputted to the slave latch connecting to the master latch.
However, in conventional master and slave latch circuits, even in the case that data is not required to be inputted, the second clock is continuously supplied to the slave latch. Since the power consumption of a semiconductor integrated circuit depends on the current that charges or discharges a load capacity, when the first clock is not supplied to a master latch, the load connected to the first clock that controls the master latch is reduced, and thereby the operating power consumption of a circuit that generates the first clock is reduced. However, in conventional master and slave latch circuits, as the second clock is continuously supplied to all the slave latches, the load connected to the second clock that controls the slave latch does not change, thereby wastefully consuming the power in the circuit that generates the second clock. This has been a problem of obstructing to lower the power consumption of semiconductor integrated circuits.